1. Technical Field
Embodiments of the disclosed invention are directed to an embedded wafer level package for a semiconductor device, and in particular, to such a device that includes through-connections extending through a package wafer of the device.
2. Description of the Related Art
For manufacturers of semiconductor devices, there is a continuing pressure to increase the density and reduce the size of the devices, so that more devices can be made on a single wafer of semiconductor material, and so that products that incorporate the devices can be made more compact. One response to this pressure has been the development of chip scale packaging and wafer level packaging. These are packages that have a footprint that is very close to the actual area of the semiconductor die. They are generally direct surface mountable, using, e.g., ball grid arrays [BGAs] and flip chip configurations.
Another development is the reconfigured wafer, or reconstituted wafer, in which a semiconductor wafer is separated into individual dice, which are spaced some greater distance apart than on the original wafer and embedded in a layer of molding compound to form the reconfigured wafer. A redistribution layer is formed over the dice to relocate contact points on the new wafer. One benefit is that this provides increased area for each die for “back end” processes, such as the formation of contacts at a scale or pitch that is compatible with circuit board limitations, without sacrificing valuable real estate on the original wafer. Such packages are typically referred to as fan-out wafer level packages, because the contact positions of the original die are “fanned out” to a larger foot print. Typically, such packages are provided with a ball-grid array for coupling to a circuit board, and are referred to as embedded wafer-level ball-grid array (eWLB) packages.
A 3D package is a package in which a plurality of semiconductor dice are stacked vertically within a single package.
A package-on-package (PoP) configuration is a package that has one face configured to be coupled to a circuit board or chip carrier, and an opposite face configured to receive another semiconductor package.
An interposer is an interface structure positioned between a semiconductor device and another element to which the device is coupled. The interposer provides routing of electrical contacts from one side to the other for proper connection.